I'm looking for Physical Design Manager for a Taiwanese MNC based in Singapore.
The job will be based in Singapore itself.
Job Responsibilities:
- In Charge of Digital Back-end Physical Design & automation.
- Main responsibilities include circuit synthesis, physical synthesis, static timing analysis, chip floorplanning, auto place and route, capacitance and resistance extraction, design rule checking and delay back-annotation.
- Responsible for clock tree synthesis, scan chain generation, critical path timing analysis and power analysis.
- DRC/LVS command file writing and maintenance.
- Leading a team of approximately 10 people.
Requirements:
- BS or above with major in EE or Computer Science related field.
- At least 5 years experience in Physical Design.
- Familiar with floorplan, placement/routing, CTS, and LVS/DRC design flow and capable of running projects independently.
- Experience with timing driven design flow preferred.
- Experience with DSM IC design or process, and familiar with device modeling, crosstalk, IR drop analysis, CMOS (65nm & 90nm) preferred.
- Experience in Leadership, project implementation, and physical verification will be a good advantage.
Anyone interested with the job?
If you are interested, just drop me an email at: felicia@uniconnect.com.sg
Thank you.
Have a nice day~
